ULX3S (ECP5 FPGA) first look.

I’ve been wanting to try project Trellis out for a little while now, I was impressed with the open source toolchain for the ICE40, however the ECP5 has everyones favourite feature (MOAR!) it’s basically bigger and faster – what’s not too love.

There is a slight issue with the current state of the toolchain, but more about that later, first lets look at some of the feature specific to the ULX3S.

I’d got wind of a new version of the ULX3S featuring the 85K LUTs version of the ECP5 and I was going to wait, until I realised that even the 45K version has way more LUTs than I’ll probably ever use! So I ended up getting the 45K version… (to get an idea of size you can simulate a full Amiga system on the 12F version!)

You probably won’t be surprised to learn that initially setting up such a complex board can be a little bit of a trial, that said once you have all the needed tools compiled, its not an impossible task.

For me one of the major features is the ESP32, while the 45K version doesn’t actually come with one soldered on, Goran very kindly soldered one on for me! While there is a minimal web back-end to program the FPGA with, it refused to connect to my router, while I could connect to the ESP32 in AP mode this is far from ideal. Fortunately there is a much better method, Micro Python to the rescue – this is definitely the way to go. Having set up lighttpd on my laptop I can use webrepl to issue

ecp5.program("http://192.168.0.40/blink.bit")

Which works very quickly and means I can have the actual board setup next to a spare monitor on my workbench while pretending to watch soaps with my wife! If you tweak a design then reprogramming is just a case of pressing up and enter in webrepl and this can very probably all be driven from a Makefile (at some point I need to learn about sending raw repl commands via python on my laptop….)

Now to the issue with the toolchain, while waiting for my board to arrive I started playing with a verilog Z80, this works great in simulation, however I noticed some issues when attempting to get it working on the hardware

Warning: Yosys has only limited support for tri-state logic at the moment.

I think this is the cause of….

ERROR: timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc.

Alas trying to ignore this with –ignore-loops while it does “compile” unsurprisingly doesn’t make it work….

I anticipate that at some point yosys may well support tri-state logic, but for now there is a whole giant heap of stuff to play with that doesn’t need tri-state logic, I think the only reason this particular softcore is using tri-state is because it’s trying to be as hardware accurate as possible…

On the subject of trying stuff out there are some fantastic examples specifically for the ULX3S, these work with the open source toolchain and props to Emard for his amazing job!

All in all this little board is literally crammed with features and in my initial look I have barely grazed the surface, neat things like the esp32 and even the DVI socket (not to mention the 32M SDRAM) make this board both very capable and useful, plenty of fun hacking ahead!

Leave a Reply

Your email address will not be published. Required fields are marked *