I’ve got a tonne of use out of the icestorm project, with it fitting into the way I work really well…
I’ve ended up putting together a simple Makefile that I use when starting a new project, simple rules allow the project to be compiled and even allow you to directly program the fpga’s cram for much faster (but volatile) programming. While targeting the ice40hx8k breakout board you could easily modify it for one of the plethora of ice40 boards out there…
here’s the Makefile
# project name also the name of the top module NAME = count # any changes in a .v file triggers the blif rule SRC := $(shell find . -name '*.v') all: $(NAME).bin prog: $(NAME).bin iceprog $< prog-ram: $(NAME).bin iceprog -S $< $(NAME).bin: $(NAME).asc icepack $< $@ $(NAME).asc: $(NAME).blif arachne-pnr -q -d 8k -P ct256 -p pins.pcf $< -o $@ $(NAME).blif: $(SRC) yosys -q -Q -p "synth_ice40 -blif $@" $(NAME).v clean: rm -f $(NAME).bin rm -f $(NAME).asc rm -f $(NAME).blif
You might occasionally want to remove the -q param from the yosys command if you want to get an idea of what real estate you’re using.
You’ll also need a constrains file (pins.pcf) here’s a simple one
set_io LEDS B5 set_io LEDS B4 set_io LEDS A2 set_io LEDS A1 set_io LEDS C5 set_io LEDS C4 set_io LEDS B3 set_io LEDS C3 set_io clk J3
Here’s a simple bit of verilog to drive these pins… (count.v)
module count(input clk,output [7:0] LEDS); reg [26:0] count; assign LEDS = count[26:19]; always @(posedge clk) begin count <= count + 1; end endmodule
…that’s it! a basic skeleton project that you can use to kick start your own projects.
all you need is the icestorm tools but thats a very simple case of cloning three projects and running make && make install (refreshingly the install really is that simple!)